Currently, in the 3GPP (3rd Generation Partnership Project), LTE (Long Term Evolution) is under study with a view to dramatically improving high-speed data rate and frequency usage efficiencies and realizing low latency in order to cope with rapidly increasing multimedia traffic. In LTE, OFDMA (Orthogonal Frequency Division Multi Access) is employed as a wireless access scheme and improvements are being made on the performance (see 3GPP TS36.300 V8.5.0 (2008-05), 3GPP TS36.321 V8.2.0 (2008-05), and 3GPP TS36.211 V8.3.0 (2008-05), for example).
In wireless communication systems employing OFDMA, system bandwidth (subcarriers) may be widened in order to increase a maximum number of users to be handled or to raise the communication rate. In wireless communication systems wherein various system bandwidths exist, wireless base stations are previously implemented with the capacity to process a maximum system bandwidth so as to be able to cope with the various system bandwidths of the different wireless communication systems.
FIG. 29 is a block diagram of a wireless interface in a wireless base station. As illustrated in FIG. 29, the wireless interface of the wireless base station includes a Layer 2 processor 501 and a Layer 1 processor 502.
The Layer 2 processor 501 processes signals at the Data Link Layer and controls, for example, radio links and the allocation of radio resources. The Layer 1 processor 502 processes signals at the Physical Layer and performs, for example, baseband processing such as channel coding, modulation, and subcarrier mapping.
To enable a wireless base station to operate over a wide system bandwidth, devices having high processing capability and thus expensive are often used as the Layer 2 and Layer 1 processors 501 and 502. Where devices with moderate processing capability are used in order to prevent increase in cost, an additional circuit block including Layer 2 and Layer 1 processors 501 and 502 is often used.
Meanwhile, there has been provided a transmitter in which a plurality of subcarriers to be subjected to IDFT (Inverse Discrete Fourier Transformation) are divided into groups so that an oversampling process can be performed to make it unnecessary to increase the sampling frequency of digital-to-analog and analog-to-digital converters (see Japanese Laid-open Patent Publication No. 2003-224538, for example).
In cases where the circuit block including Layer 2 and Layer 1 processors is added in order to widen the system bandwidth, however, a problem arises in that since parameters are exchanged between the circuit blocks, the signal processing capability lowers due to increased load on the bus.
FIG. 30 illustrates the manner of how parameters are exchanged between layer processors. Compared with the wireless interface of FIG. 29, a wireless interface illustrated in FIG. 30 is additionally provided with a Layer 2 processor 511 and a Layer 1 processor 512 in order to process twice the system bandwidth.
In this case, the Layer 2 processors 501 and 511 exchange parameters with each other to determine, for example, the manner of how radio resources out of the entire system bandwidth are to be allocated to users. Also, the Layer 2 processors 501 and 511 exchange parameters with the Layer 1 processors 512 and 502, respectively, to determine the manner of how channel coding is to be executed within the entire system bandwidth. Consequently, the load on the bus increases, lowering the signal processing capability.